Two common issues that come up when attempting to run an algorithm on specific hardware platforms include:

  1. Gates inside of theoretical circuits are not directly compatible with the hardware’s native gateset.

  2. Gates or circuits are specified as unitary matrices, rather than specific gate decompositions.

If True-Q™ has access to the configuration of the system, it is possible to solve both of these issues. Our compilation tools take a circuit and rewrite it using only the gates and connections specified in a given device configuration file.



The same circuit can be transpiled for implementation on any number of hardware devices. Below we show an example of this.

How it Works

True-Q™ has a number of compilation tools which rely upon device-specific configurations. The compilation tools work by applying an ordered list of built-in and/or user-specified Patterns to a circuit in order, see (Compiler for more details).

To give a feel for what a compiler definition looks like, here is the list of patterns that defines the default compiler which is used when no custom list of Patterns is provided:

import trueq as tq
 functools.partial(<class 'trueq.compilation.common.RemoveId'>, skip_immutable=False),

Each item in the list above is one of True-Q™’s built-in Patterns. Notice that RemoveId is applied twice; this is because the patterns in a compiler are applied sequentially and in the order listed above it is possible that new identity gates may have appeared between the first application of RemoveId and the second.

Each pattern takes a specific number of cycles, applies an operation to them, and returns an altered list of cycles. Details of how this functions can be found in Compiler.

Here are the premade Patterns available for use with the compiler:


Pattern that searches Circuits for a specific Cycle and when found, sandwiches it between two other (optional) cycles.


Decomposes single qubit gates into 3 gates \(R(\theta) R(\phi) Z(\gamma)\), where the R gates are defined by \(Z(\theta) X(90) Z(-\theta)\).


A pattern which ensures that any NativeGate that is defined from a Config obeys the involving restrictions of its GateFactorys.


Pattern that takes two Cycles, and moves gates preferentially to one side.


Pattern that takes two cycles, finds compatabile labels and gates, then merges them to a single gate as much as is possible.


Pattern which expands arbitrary single qubit gates into the decomposition mode provided in a given Config object.


Series of numerical SU(4) decomposition methods.


This pattern tracks phase accumulation on each qubit throughout a circuit, and compiles this phase information into parametric gates.


Pattern which relabels all the labels and keys in a Circuit.


Pattern that removes identity gates from 1 Cycle.



Compiler: Converting to a Gateset


Phase Tracking with the Compiler


Gate synthesis